Due to the rapid advancement of semiconductor processes and the maturity of sub-5GHz RF design, there has been increasing interest in the higher-frequency, mm-wave (30GHz to 300GHz) and THz (300GHz to 3THz) regime. The higher carrier frequency enables exciting new applications such as automotive radar, 5G, WiGig, and IoT. The main challenges at these frequencies include how to miniaturize systems for mobile applications, how to generate enough power to compensate for the high loss, as well as how to form a narrow beamwidth to improve the resolution in imaging systems.
In this thesis, we present the design of a Wirelessly Synchronized Multi-chip Array (WSMA) in 65-nm CMOS. The proposed architecture makes use of a central wireless signal to synchronize a mm-wave array, eliminating the need for connecting wires between the array elements. Wireless injection locking of a single chip is successfully demonstrated and a 3-dB linewidth of 400 Hz at a carrier frequency of 50 GHz is achieved (stability ratio of 8 ppb). In addition, a 2-element WSMA with an array aperture greater than 20 wavelengths is demonstrated using the proposed transceiver architecture. The reported transceiver includes a receiving on-chip antenna, a low-noise amplifier, an injection-locked voltage-controlled oscillator, a buffer amplifier, an in-phase/quadrature generator, a phase shifter, a power amplifier, and a transmitting on-chip antenna. The chip is fabricated in a 65-nm CMOS process and occupies an area of 1.7 mm × 3.8 mm. This work sets the foundation for increasing the array aperture through wireless injection locking, extending traditional array systems into the high-resolution, narrow-beamwidth regime.